The microelectronics industry, owes its success to the relentless technological progress of the micro-fabrication processes. These fabrication processes have allowed the critical dimensions of electronic devices be decreased to the deep submicrometer levels. In this size range, the MISFET (Metal-Insulator-Semiconductor-Field Effect Transistor) and preferably the MOSFET (Metal-Oxide Semiconductor-Field-Effect-Transistor) device is the preferred type of device, because it offers the best compromise between speed, size, power dissipation, and production cost.
Lithography has been the technology driver of all other processing steps. In fact, it has been the limitation for making smaller transistors, because the other process steps could easily be scaled to smaller dimensions.
The advantages of patterning smaller features are twofold: smaller design rules, for a given area, mean more devices, and smaller devices are faster and dissipate less power.
Up to now, very small planar transistors are fabricated with experimental techniques which are not suitable for production. It is not yet clear if they will ever be. There are also device physics problems for their operation at room temperature. Because the issues being faced now are of unprecedented difficulty, the evolutionary approach (or incremental engineering) seems unable to deliver solutions for at least some of the problems. These problems are of different natures: device physics, new fabrication techniques demanding new types of processing equipment, and economics.
Making Si MISFET devices with short gates (e.g. less than 0.12 .mu.m), presents (in 1995) two very obvious problems: device physics and fabrication technology.
The first problem is known as Drain Induced Barrier Lowering (DIBL), which, for very short channels exists even without drain bias. This effect, results in undesirable high off-state currents, which will have a major contribution to serious power dissipation problems. It also degrades the switching properties (sub threshold current slope) of the devices.
Lithography and shallow junction formation are the most prominent fabrication technologies. Although, from the technical point of view, several proposed solutions seem to work, they imply different fabrication techniques, using new types of equipment. For some of these techniques, it is not yet clear if they will ever be economically feasible. This is clearly the case with lithography technologies for dimensions below 0.12 .mu.m.
To solve the technological problems, Vertical MISFET devices have been proposed. In this way, the lithographic steps define the cross section of the transistor, and the gate/channel length will be defined by epitaxial techniques (at low temperatures).
In fact, Planar Delta Doped Vertical MISFET devices having a homojunction are known.
However, the DIBL effect remains for these devices, thereby imposing a minimum channel length. This results from the fact that potential barriers built by doping suffer from charge redistribution when a bias is applied, and their maximum value is limited by the band-gap of Si. Also, very short distances between source/drain and the delta doped barrier results in a strong field, enhancing band to band tunnelling beyond acceptable levels.
U.S. Pat. No. 4,740,826 describes a Vertical Complementary Metal Oxide Semiconductor (CMOS) inverter fabricated by forming a layer of P-type material on the surface of an N+-type substrate followed by formation of an N+ layer, a P+ layer, an N- layer and a P+ layer. A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. In addition, another trench is formed to create a gate insulator and a- gate. There is only homojunction between the several layers.
Transistors having a heterojunction have been described as "Fabrication of Three-terminal Resonant Tunnelling Devices in Silicon-based Material" of A. Zaslavsky, K. R. Milkove, Y. H. Lee, K. K. Chan, F. Stern, D. A. Grutzmacher, S. A. Rishton, C. Stanis, and T. O. Sedgwick: Appl. Phys. Lett. 64 (13), Mar. 28, 1994.
This reference describes the fabrication of a silicon-based device having a double SiGe barrier for which the physical principle of operation is resonant tunnelling.
U.S. Pat. No. 4,550,489 describes a Vertical Field Effect Transistor wherein the layer structure is formed epitaxially and wherein the gate is formed by a Schottky junction between a metal electrode and the channel semiconductor material. The current control mechanism is barrier thinning to enhance tunnelling across the channel material.
U.S. Pat. No. 4,236,166 describes a Vertical Field Effect Transistor which includes a relatively wide bandgap, lowly doped active layer epitaxially grown on, and substantially lattice matched to, an underlying semiconductor body portion. A mesa of lower bandgap material is epitaxially grown on and substantially lattice matched to the active layer. A source electrode is formed on a bottom major surface of the semiconductor body portion, a drain electrode is formed on the top of the mesa, and a pair of gate electrode stipes are formed on the active layer adjacent both sides of the mesa.
This transistor is normally on and needs the application of a gate voltage to turn off. This turn-off mechanism works through the depletion of channel material to stop current which imposes, in the present case, constraints on the lateral to vertical dimension ratio.
The "GEC Journal of Research, 10 (1993) no. 3, pp. 645, Chelmsford, Essex, GB, describes very well known technique used for epitaxially grown Si and Si.sub.1-x Ge.sub.x heterostructure. However, there is no mention of vertical MISFET transistors in this document.
Currently CMOS process integration using Vertical MISFETs faces four main problems:
a) Requirements of multiple epitaxial runs to make complementary transistors. In process architectures where complementary transistors are made sequentially, at least two epi-runs (SEGs even), have to be performed. This implies process complexity, low temperature cleans and cures, very selective etches, etc. PA1 b) Parasitic capacitances coming from extensive gate overlap of highly doped regions. The gate fully overlaps the source and drain (which is something that doesn't happen with planar transistors). This capacitance can be significative since "thick" source and drain layers should be provided for minimization of the series resistance. PA1 c) Extensive gate overlap. When gate electrode definition is made by lithography and dry etch, there are even more extensive regions overlapped by the gate electrode: on top of the transistor itself, and on the highly doped layer where the vertical transistor was defined. The latter is unavoidable if the contact to that layer is made outside the perimeter defined by the gate. PA1 d) Low integration density resulting from the necessity of separately contacting layers on different levels. In the age of self-aligned planar MOSFETs, one patterning step results in the contacts for all the terminals of the transistors. With vertical transistors where contacts have to be made with 2 or 3 patterning steps, area has to be provided for the inaccuracy of the alignments from one layer to the other. These built-in tolerances can cause a large area penalty (lithography tools have a non-zero alignment accuracy). PA1 a) The channel layer is undoped or lowly doped; PA1 b) A heterojunction is formed between the source, and the channel with an undoped or lowly doped region in the source near the source/channel interface, and PA1 c) A gate is overlapping, preferably essentially at a right angle, at least partially the source, the channel and the drain layers with an insulate layer therebetween. PA1 a) The drain comprises a highly doped p++ layer preferably Si layer. PA1 b) The channel is an undoped layer (preferably Si). PA1 c) The source comprises at least a double layer consisting of an undoped or lowly doped Si.sub.1-x Ge.sub.x layer and a highly doped p++ possibly graded SiGe layer. PA1 a) The drain comprises a highly doped n++ layer preferably Si layer. PA1 b) The channel is an undoped layer (preferably Si). PA1 c) The source comprises at least a double layer consisting of an undoped or lowly doped Si.sub.1-x-y Ge.sub.x C.sub.y or S.sub.1-y C.sub.y layer and a highly doped n++ possibly graded Si.sub.1-x-y Ge.sub.x C.sub.y or Si.sub.1-y C.sub.y layer. PA1 a) The drain comprises a highly doped n++ layer (preferably Ge). PA1 b) The channel is an undoped layer (preferably Ge). PA1 c) The source comprises at least a double layer consisting of an undoped or lowly doped Si.sub.1-y Ge.sub.y layer and a highly doped n++ possibly graded SiGe layer. PA1 a) one epitaxial deposition sequence on a silicon substrate is used for defining the several layers of each Vertical MISFET device possibly stacked, PA1 b) a patterning step consisting of a lithographic/etch step is used to create the surrounding gate around the possibly stacked device(s), and PA1 c) other patterning steps are used to make contact to the source and to the drain of each Vertical MISFET device possibly stacked. PA1 a) Epitaxy of Several Layers of a Vertical MISFET device; PA1 b) Deposition of the Insulator(s); PA1 c) Mask 1: Definition of Configuration units (MESAS) each corresponding to one stack; PA1 d) Formation of Gate Electrode on Mesas Sidewalls; PA1 e) Gate Electrode Etchback (Spacer-like Electrode); PA1 f) Planarization: Filling of Spaces Between Mesas; PA1 g) Mask 2: Formation of Gate Contact Pad; PA1 h) Mask 3: (Common) Drain Contact Holes PA1 i) Formation of Spacers at least Partially on the Internal Side Walls of the Top/Bottom Device; PA1 j) Contact Hole Filling with Silicide & Metal; PA1 k) Mask 4: Contact Hole to Source of Top Device; PA1 l) Contact Hole Filling with Silicide & Metal; PA1 m) Metallization. PA1 a) a channel layer which is undoped or lowly doped; PA1 b) a heterojunction which is formed between the source and the channel with a presence of an undoped or lowly doped region in the source near the source/channel interface, and PA1 c) a gate which is overlapping, preferably essentially at right angle, at least partially the source, the channel, and the drain layers with an insulate layer there between.
Historically, Dynamic Random Access Memory (DRAM) has been the product driving the advances in micro-fabrication.
DRAMs have got more bits per die, due to the combined effects of ever smaller lateral features, and to ever larger dies. Even these two factors are by no means certain to work in the future. It is uncertain what kind of lithography equipment will provide resolution below 0.1 .mu.m. Since die size is dependent on the lithography tool used, the answer to the first question will also provide the answer to the second.
In any case, it seems that the factors of progress which worked so well in the past, will fail to do so for the Gigabit age. New approaches are needed to continue the accelerated pace of the past, into the future.
A Random Access Memory (RAM) cell, needs at least one transistor and one charge storage capacitor. Therefore, it is dependent on how small the transistor (usually a MOSFET) can be made. The planar MOSFET, when reducing the lateral dimensions, needs to have very shallow junctions, with low leakage currents. This is a difficult problem, as the 0.12 .mu.m generation is approached. This is very important, because the charge retention in the capacitor is dependent on the leakage current of the transistor. The larger the leakage, the higher the refreshment rate the capacitor needs to be, in order to preserve the stored information.
The capacitor itself is also a concern. As the lateral dimensions of the capacitor are reduced, so is the total capacitance. Also, operating voltages need to be reduced, but there is a minimum of charge that must be stored, because noise is determined by KT, which is a fixed value. The solution for this problem has been to increase the capacitance per area by thinning the silicon dioxide between the capacitor plates, and by fabricating three dimensional capacitor structures. However, the silicon dioxide cannot be scaled beyond the value at which leakage current becomes prohibitive. Three dimensional capacitor structures can increase the effective capacitor area, without increasing the footprint of the cell, but introduce important process complexities, which in turn, tend to decrease the yield. It seems that the future of capacitors lies with planar structures using dielectric materials with large permeability values.
If SOI substrates were used, MISFET leakage current would be strongly reduced. However, SOI requires costly substrates.